This invention relates to the field of field emission devices, or "FED's."
FED's are used in the manufacture of flat panel displays and comprise, as seen in U.S. Pat. No. 3,970,887, incorporated herein by reference, an emitter tip and a gate formed on a substrate. A voltage potential between the emitter (which comprises a cathode) and an anode located in the area of a phosphor (not shown), generates an electron stream from the emitter which causes the phosphor to emit light. Pixels of the display comprise multiple emitter tips which are controlled by gates (designated in FIG. 1G of the '887).
One acceptable way to interconnect the pixels of the display is to form the pixels on rows of N-doped silicon, as seen in FIG. 6 of the '887 patent. Subsequent processing lays transverse strips of metal to serve as the gate, as seen in FIG. 7 and FIG. 8 of the '887 patent. Other examples of interconnection of pixels are seen in U.S. Pat. Nos. 5,374,868 and 5,212,426, both of which are incorporated herein by reference.
One problem in the manufacture of these devices, however, is the need for specific masking steps to make the N-well--steps separate from those needed to form other parts of the device. Further, traditional N-well's in such devices are not "self-aligned" with the other components of the device, thus creating alignment error and limiting the reduction in pixel size needed to achieve high resolution displays. Further still, non-self-aligned processes are complex and costly.
Therefore, it is an object of the present invention to address these problems.